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this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 1.0 / apr. 2005 1 240pin registered ddr2 sdram dimms based on 1gb 1st ver. this hynix registered dual in-line memory module (dimm) series consists of 1gb first version ddr2 sdrams in fine ball grid array(fbga) packages on a 240pin glass-epoxy substrate. this hynix 1 gb 1st ver. based registered ddr2 dimm series provide a high performance 8 byte inte rface in 5.25" width form factor of industry standard. it is suitable for easy interchange and addition. features ordering information part name density organization # of drams # of ranks materials hymp112r728-e3/c4 1gb 128mx72 9 1 leaded hymp125r728-e3/c4 2gb 256mx72 18 2 leaded hymp125r724-e3/c4 2gb 256mx72 18 1 leaded hymp351r72m4-e3/c4 4gb 512mx72 36 2 leaded hymp112r72p8-e3/c4 1gb 128mx72 9 1 lead free hymp125r72p8-e3/c4 2gb 256mx72 18 2 lead free hymp125r7p24-e3/c4 2gb 256mx72 18 1 lead free hymp351r72mp4-e3/c4 4gb 512mx72 36 2 lead free ? jedec standard double data rate2 synchronous drams (ddr2 sdrams) with 1.8v +/- 0.1v power supply ? all inputs and outputs are compatible with sstl_1.8 interface ?8 bank architecture ?posted cas ? programmable cas latency 3 , 4 , 5 ? ocd (off-chip driver impedance adjustment) ? odt (on-die termination) ? fully differential clock operations (ck & /ck) ? programmable burst length 4 / 8 with both sequen- tial and interleave mode ? auto refresh and self refresh supported ? 8192 refresh cycles / 64ms ? serial presence detect with eeprom ? ddr2 sdram package: 68ball fbga ? 133.35 x 30.00 mm form factor ? lead-free products are rohs compliant
rev. 1.0 / apr. 2005 2 1 240pin registered ddr2 sdram dimms speed grade & key parameters address table e3 (ddr2-400) c4 (ddr2-533) unit speed@cl3 400 400 mbps speed@cl4 400 533 mbps speed@cl5 400 533 mbps cl-trcd-trp 3-3-3 4-4-4 tck organization ranks sdrams # of drams # of row/bank/column address refresh method 1gb 128m x 72 1 128mb x 8 9 14(a0~a13)/2 (ba0~ba2)/10(a0~a9) 8k / 64ms 2gb 256m x 72 2 128mb x 8 18 14(a0~a13)/2(ba0~ba2)/10(a0~a9) 8k / 64ms 2gb 256m x 72 1 256mb x 4 18 14(a0~a13)/2(ba0~ba2)/11(a0~a9,a11) 8k / 64ms 4gb 512m x 72 2 256mb x 4 36 14(a0~a13)/2(ba0~ba2)/11(a0~a9,a11) 8k / 64ms
rev. 1.0 / apr. 2005 3 1 240pin registered ddr2 sdram dimms input/output functional description symbol type polarity pin description ck0 in positive edge positive line of the differential pair of system clock inputs that drives input to the on-dimm pll. ck 0in negative edge negative line of the differential pair of system clock inputs that drives input to the on-dimm pll. cke[1:0] in active high activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deac- tivating the clocks, cke low initiates the po wer down mode or the self refresh mode. s [1:0] in active low enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations con- tinue. rank 0 is selected by s 0; rank 1 is selected by s 1 odt[1:0] in active high on-die termination signals. ras , cas , we in active low when sampled at the positive rising edge of the clock. ras ,cas and we (along with s) define the command being entered. vref supply reference voltage for sstl18 inputs v ddq supply power supplies for the ddr2 sdram output buffer s to provide improved noise immunity. for all current ddr2 unbuffered dimm designs, v ddq shares the same power plane as v dd pins. ba[2:0] in - selects which ddr2 sdram internal bank of eight is activated. a[9:0], a10/ap a[13:11] in - during a bank activate command cycle, address input difines the row address(ra0~ra13) during a read or write command cycle, address input defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge oper ation at the end of the burst read or write cycle. if ap is high., autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle., ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. dq[63:0], cb[7:0] in - data and check bit input/output pins. dm[8:0] in activ high dm is an input mask signal for write data. input data is masked when dm is sampled high coinci- dent with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loadin g matches the dq and dqs loading. v dd ,v ss supply power and ground for the ddr2 sdram input buffers, and core logic. v dd and v ddq pins are tied to v dd /v ddq planes on these modules. dqs[17:0] i/o positive edge positive line of the differential data strobe for input and output data dqs[ 17:0] i/o negative edge negative line of the differential da ta strobe for inpu t and output data sa[2:0] in - these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range. sda i/o - this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resister may be connected from the sda bus line to v ddspd on the system planar to ac t as a pull up. scl in - this signal is used to clock da ta into and out of the spd eeprom. a resistor may be connected from scl to v ddspd to act as a pull up on the system board. vddspd supply power supply for spd eeprom. this supply is separate from the vdd/vddq power plane. eeprom supply is operable from 1.7v to 3.6v. reset in the reset pin is connected to the rst pin on the register and to the oe pin on the pll. when low, all register outputs will be driven lo w and the pll clocks to the drams and register(s) will be set to low level (the pll will remain synchronized with the input clock) par_in in parity bit for the address and control bus(?1?. odd, ?0?.even) err_out out parity error found in the address and control bus test used by memory bu s analysis tools(unus ed on memory dimms)
rev. 1.0 / apr. 2005 4 1 240pin registered ddr2 sdram dimms pin description pin location pin pin description pin pin description ck0 clock input,positive line odt[1:0] on die termination inputs ck 0 clock input,negative line vddq dqs power supply cke0~cke1 clock enable input dq0~dq63 data input/output ras row address strobe cb0~cb7 data check bits input/output cas column address strobe dqs(0~8) data strobes we write enable dqs (0~8) data strobes,negative line s 0,s 1 chip select input dm(0~8),dqs(9~17) data maskes/data strobes a0~a9,a11~a13 address input dqs(9~ 17) data strobes,negative line a10/ap address input/autoprecharge rfu reserved for future use ba0, ba1, ba2 sdram bank address nc no connect scl serial presence detect(spd) clock input test memory bus test tool (not connected and not usable on dimms) sda spd data input/output vdd core power sa0~sa2 e 2 prom address inputs vddq i/o power par_in parity bit for the address and control bus vss ground err_out parity error found on the addre vref input/output reference reset reset enable vddspd spd power cb0~cb7 data check bit inputs/outputs 1 pin front side 64 pin 65 pin 120 pin 121 pin back side 184 pin 185 pin 240 pin
rev. 1.0 / apr. 2005 5 1 240pin registered ddr2 sdram dimms pin assignment nc= no connect, rfu= reserved for future use. note: 1. reset(pin 18) is connected to both oe of pll and reset of register. 2. nc/err_out (pin 55) and nc/par_in(pin68) are for op tional function to check address and command parity. 3. the test pin(pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(dimms) pin name pin name pin name pin name pin name pin name 1 vref 41 vss 81 dq33 121 vss 161 cb4 201 vss 2 vss 42 cb0 82 vss 122 dq4 162 cb5 202 dm4/dqs13 3dq043cb183dqs 4 123 dq5 163 vss 203 dqs 13 4 dq1 44 vss 84 dqs4 124 vss 164 dm8,dqs17 204 vss 5vss45dqs 8 85 vss 125 dm0/dqs9 165 dqs 17 205 dq38 6dqs 046 dqs8 86 dq34 126dqs 9 166 vss 206 dq39 7 dqs0 47 vss 87 dq35 127 vss 167 cb6 207 vss 8 vss 48 cb2 88 vss 128 dq6 168 cb7 208 dq44 9 dq2 49 cb3 89 dq40 129 dq7 169 vss 209 dq45 10 dq3 50 vss 90 dq41 130 vss 170 vddq 210 vss 11 vss 51 vddq 91 vss 131 dq12 171 nc,cke1 211 dm5/dqs14 12 dq8 52 cke0 92 dqs 5 132 dq13 172 vdd 212 dqs 14 13 dq9 53 vdd 93 dqs5 133 vss 173 a15,nc 213 vss 14 vss 54 ba2,nc 94 vss 134 dm1/dqs10 174 a14,nc 214 dq46 15 dqs 155nc,err_out 95 dq42 135 dqs 10 175 vddq 215 dq47 16 dqs1 56 vddq 96 dq43 136 vss 176 a12 216 vss 17 vss 57 a11 97 vss 137 rfu 177 a9 217 dq52 18 reset 58 a7 98 dq48 138 rfu 178 vdd 218 dq53 19 nc 59 vdd 99 dq49 139 vss 179 a8 219 vss 20 vss 60 a5 100 vss 140 dq14 180 a6 220 rfu 21 dq10 61 a4 101 sa2 141 dq15 181 vddq 221 rfu 22 dq11 62 vddq 102 nc(test) 142 vss 182 a3 222 vss 23 vss 63 a2 103 vss 143 dq20 183 a1 223 dm6/dqs15 24 dq16 64 vdd 104 dqs 6 144 dq21 184 vdd 224 nc,dqs 15 25 dq17 key 105 dqs6 145 vss key 225 vss 26 vss 65 vss 106 vss 146 dm2/dqs11 185 ck0 226 dq54 27 dqs 2 66 vss 107 dq50 147 dqs 11 186 ck 0227dq55 28 dqs2 67 vdd 108 dq51 148 vss 187 vdd 228 vss 29 vss 68 nc,err_out 109 vss 149 dq22 188 a0 229 dq60 30 dq18 69 vdd 110 dq56 150 dq23 189 vdd 230 dq61 31 dq19 70 a10/ap 111 dq57 151 vss 190 ba1 231 vss 32 vss 71 ba0 112 vss 152 dq28 191 vddq 232 dm7/dqs16 33 dq24 72 vddq 113 dqs 7 153 dq29 192 ras 233 nc,dqs 16 34 dq25 73 we 114 dqs7 154 vss 193 s 0234 vss 35 vss 74 cas 115 vss 155 dm3/dqs12 194 vddq 235 dq62 36 dqs 3 75 vddq 116 dq58 156 dqs 12 195 odt0 236 dq63 37 dqs3 76 nc, s 1 117 dq59 157 vss 196 a13,nc 237 vss 38 vss 77 nc, odt1 118 vss 158 dq30 197 vdd 238 vddspd 39 dq26 78 vddq 119 sda 159 dq31 198 vss 239 sa0 40 dq27 79 vss 120 scl 160 vss 199 dq36 240 sa1 80 dq32 200 dq37
rev. 1.0 / apr. 2005 6 1 240pin registered ddr2 sdram dimms functional block diagram 1gb(128mbx72) : hymp112r72[p]8 p l l oe pck0 to pck6, pck8,pck9 ==> ck: sdrams d0 tod8 /pck0 to /pck6, /pck8, /pck9 ==> /ck: sdrams d0 tod8 pck7 ==> ck: register /pck7 ==> /ck: register ck0 /ck0 /reset /rs0 d0 dq0 i/o 0 dq1 i/o 1 dq2 i/o 2 dq3 i/o 3 dq4 i/o 4 dq5 i/o 5 dq6 i/o 6 i/o 7 dq7 /dqs0 dm0,dqs9 dqs0 /cs dqs /dqs dm rdqs nu /rdqs /dqs9 d1 dq8 i/o 0 dq9 i/o 1 dq10 i/o 2 dq11 i/o 3 dq12 i/o 4 dq13 i/o 5 dq14 i/o 6 i/o 7 dq15 /dqs1 dm1,dqs10 dqs1 /cs dqs /dqs dm rdqs nu /rdqs /dqs10 d2 dq16 i/o 0 dq17 i/o 1 dq18 i/o 2 dq19 i/o 3 dq20 i/o 4 dq21 i/o 5 dq22 i/o 6 i/o 7 dq23 /dqs2 dm2,dqs11 dqs2 /cs dqs /dqs dm rdqs nu /rdqs /dqs11 d3 dq24 i/o 0 dq25 i/o 1 dq26 i/o 2 dq27 i/o 3 dq28 i/o 4 dq29 i/o 5 dq30 i/o 6 i/o 7 dq31 /dqs3 dm3,dqs12 dqs3 /cs dqs /dqs dm rdqs nu /rdqs /dqs12 d8 cb0 i/o 0 cb1 i/o 1 cb2 i/o 2 cb3 i/o 3 cb4 i/o 4 cb5 i/o 5 cb6 i/o 6 i/o 7 cb7 /dqs8 dm8dqs17 dqs8 /cs dqs /dqs dm rdqs nu /rdqs /dqs17 d4 dq32 i/o 0 dq33 i/o 1 dq34 i/o 2 dq35 i/o 3 dq36 i/o 4 dq37 i/o 5 dq38 i/o 6 i/o 7 dq39 /dqs4 dm4,dqs13 dqs4 /cs dqs /dqs dm rdqs nu /rdqs /dqs13 d5 dq40 i/o 0 dq41 i/o 1 dq42 i/o 2 dq43 i/o 3 dq44 i/o 4 dq45 i/o 5 dq46 i/o 6 i/o 7 dq47 /dqs5 dm5,dqs14 dqs5 /cs dqs /dqs dm rdqs nu /rdqs /dqs14 d6 dq48 i/o 0 dq49 i/o 1 dq50 i/o 2 dq51 i/o 3 dq52 i/o 4 dq53 i/o 5 dq54 i/o 6 i/o 7 dq55 /dqs6 dm6,dqs15 dqs6 /cs dqs /dqs dm rdqs nu /rdqs /dqs15 d7 dq56 i/o 0 dq57 i/o 1 dq58 i/o 2 dq59 i/o 3 dq60 i/o 4 dq61 i/o 5 dq62 i/o 6 i/o 7 dq63 /dqs7 dm7,dqs16 dqs7 /cs dqs /dqs dm rdqs nu /rdqs /dqs16 vdd spd vdd / vddq vref vss serial pd do-d8 do-d8 do-d8 sa0 sa1 sa2 w p scl sda a0 a1 a2 serial pd scl u0 sda * : /s0 connects to d/cs and vdd connects to /csr on register. odt0 cke0 /pck7 /we r e g i s t e r pck7 /reset /cas /ras ba0 to ba2 a0 to a13 /cs0* rodt0 ==> odt0: sdrams d0 to d8 /rwe ==> /we: sdrams d0 to d8 rcke0 ==> cke: sdrams d0 to d8 /rcas ==>/cas: sdrams d0 to d8 /rras ==>/ras: sdrams d0 to d8 /ra0 to ra13 ==> a0 to a13: sdrams d0 to d8 rba0 to rba2 ==> ba0 to ba2: sdrams d0 to d8 /rs0 to /cs ==> /cs: sdrams d0 to d8 /rst 1. register values are 22 ohms. notes :
rev. 1.0 / apr. 2005 7 1 240pin registered ddr2 sdram dimms functional block diagram 2gb(256mbx72) : hymp125r72[p]8 z /rs0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 /rs1 /dqs1 /dqs10 dm1,dqs10 dqs1 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d1 dm rdqs nu / rdqs /cs dqs / dqs i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d10 dm rdqs nu / rdqs /cs dqs / dqs /dqs0 /dqs9 dm0, dqs9 dqs0 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d0 dm rdqs nu / rdqs /cs dqs / dqs i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d9 dm rdqs nu / rdqs /cs dqs / dqs /dqs2 /dqs11 dm2, dqs11 dqs2 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d2 dm rdqs nu / rdqs /cs dqs / dqs i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d11 dm rdqs nu / rdqs /cs dqs / dqs /dqs3 /dqs12 dm3, dqs12 dqs3 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d3 dm rdqs nu / rdqs /cs dqs / dqs i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d12 dm rdqs nu / rdqs /cs dqs / dqs /dqs8 /dqs17 dm8, dqs17 dqs8 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d8 dm rdqs nu / rdqs /cs dqs / dqs i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d17 dm rdqs nu / rdqs /cs dqs / dqs /dqs4 /dqs13 dm4, dqs13 dqs4 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d4 dm rdqs nu / rdqs /cs dqs / dqs i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d13 dm rdqs nu / rdqs /cs dqs / dqs /dqs5 /dqs14 dm5, dqs14 dqs5 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d5 dm rdqs nu / rdqs /cs dqs / dqs i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d14 dm rdqs nu / rdqs /cs dqs / dqs /dqs6 /dqs15 dm6, dqs15 dqs6 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d6 dm rdqs nu / rdqs /cs dqs / dqs i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d15 dm rdqs nu / rdqs /cs dqs / dqs /dqs7 /dqs16 dm7, dqs16 dqs7 i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d7 dm rdqs nu / rdqs /cs dqs / dqs i/ o 0 i/ o 1 i/ o 2 i/ o 3 i/ o 4 i/ o 5 i/ o 6 i/ o 7 d16 dm rdqs nu / rdqs /cs dqs / dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 odt0 cke0 /pck7 /we 1:2 r e g i s t e r pck7 /reset /cas /ras ba0 to ba2 a0 to a13 /s1 /rst /s0 rodt1 => odt1: sdrams d9-d17 odt1 cke1 rodt0 => odt0: sdrams d0-d8 rcke1 => cke1: sdrams d9-d17 rcke0 => cke0: sdrams d0-d8 /ra0 to ra12 => a0 - a12 : sdrams d0 - d17 /rwe => /we: sdrams d0-d17 /rcas => /cas: sdrams d0-d17 /rras => /ras: sdrams d0-d17 /rba0 to rba2 => ba0 - ba2 : sdrams d0 - d17 /rs1 to /cs : sdrams d9 - d17 /rs0 to /cs : sdrams d0 - d8 notes: 1. register values are 22 ohms +/- 5%. 2. /rs0 and /rs1 alternate between the back and front sides of the dimm p l l oe ck0 /ck0 /reset pck0 to pck6, pck8,pck9 => ck : sdramx d0-d17 /pck0 to /pck6, /pck8,/pck9 => /ck : sdramx d0-d17 pck7 => ck: register /pck7 => /ck: register scl sda a0 a1 wp serial pd scl sa0 sa1 sa2 a1 v dd spd v ref v dd /v ddq v ss serial pd do-d17 do-d17 do-d17
rev. 1.0 / apr. 2005 8 1 240pin registered ddr2 sdram dimms functional block diagram 2gb(256mbx72): hymp125r72[p]4 /rs0 vss d0 dqs /cs dm i/o0 i/o1 i/o2 i/o3 dq0 dq1 dq2 dq3 /dqs0 /dqs dqs0 d1 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs1 /dqs dqs1 d2 dqs /cs dm i/o0 i/o1 i/o2 i/o3 dq16 dq17 dq18 dq19 /dqs2 /dqs dqs2 d3 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs3 /dqs dqs3 d4 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs4 /dqs dqs4 d5 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs5 /dqs dqs5 d6 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs6 /dqs dqs6 d7 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs7 /dqs dqs7 d8 dqs /cs dm i/o0 i/o1 i/o2 i/o3 cb0 cb1 cb2 cb3 /dqs8 /dqs dqs8 d9 dqs /cs dm i/o0 i/o1 i/o2 i/o3 dq4 dq5 dq6 dq7 /dqs9 /dqs dqs9 d10 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs10 /dqs dqs10 d11 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs11 /dqs dqs11 d12 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs12 /dqs dqs12 d13 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs13 /dqs dqs13 d14 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs14 /dqs dqs14 d15 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs15 /dqs dqs15 d16 dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs16 /dqs dqs16 d17 dqs /cs dm i/o0 i/o1 i/o2 i/o3 cb4 cb5 cb6 cb7 /dqs17 /dqs dqs17 dq60 dq61 dq62 dq63 dq52 dq53 dq54 dq55 dq44 dq45 dq46 dq47 dq36 dq37 dq38 dq39 dq28 dq29 dq30 dq31 dq20 dq21 dq22 dq23 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq48 dq49 dq50 dq51 dq56 dq57 dq58 dq59 * /s0 connects to d/cs of register1 and /csr of register2. /csr of register and d/cs of register2 connects to vdd. ** /reset,pck7 connect to both registers. other signals connect to one of two registers. /s1,cke1 and odt1 are nc. p l l oe ck0 /ck0 /reset pck0 to pck6, pck8,pck9 = > ck : sdramx d0-d17 /pck0 to /pck6, /pck8,/pck9 = > /ck : sdramx d0-d17 pck7 = > ck: register /pck7 = > /ck: register sa0 sa1 sa2 w p scl sda a0 a1 a2 serial pd scl u0 sda v dd spd v ref v dd /v ddq v ss serial pd do-d17 do-d17 do-d17 1. resistor values are 22 ohms +/- 5%. notes: odt0 cke0 /pck7 /w e r e g i s t e r pck7 /reset /cas /ras ba0 to ba2 a0 to a13 /cs0* rodt0 ==> odt0: sdrams d0 to d17 /rwe ==> /we: sdrams d0 to d17 rcke0 ==> cke: sdrams d0 to d17 /rcas ==>/cas: sdrams d0 to d17 /rras ==>/ras: sdrams d0 to d17 /ra0 to ra13 ==> a0 to a13: sdrams d0 to d17 rba0 to rba2 ==> ba0 to ba2: sdrams d0 to d17 /rs0 to /cs ==> /cs: sdrams d0 to d17 /rst
rev. 1.0 / apr. 2005 9 1 240pin registered ddr2 sdram dimms functional block diagram 4gb(512mbx72) : hymp351r72m[p]4 /rs0 vss /rs1 dq0 dq1 dq2 dq3 dqs0 /dqs0 d0,d18( ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm /dqs dq8 dq9 dq10 dq11 dqs1 /dqs1 d1,d19( ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm /rs0 /rs1 dq16 dq17 dq18 dq19 dqs2 /dqs2 d2,d20( ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm /dqs dq24 dq25 dq26 dq27 dqs3 /dqs3 d3,d21( ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm /rs0 /rs1 dq48 dq49 dq50 dq51 dqs6 /dqs6 d6,d24(ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm /dqs dq56 dq57 dq58 dq59 dqs7 /dqs7 d7,d25( ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm /rs0 /rs1 dq32 dq33 dq34 dq35 dqs4 /dqs4 d4,d2( ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm /dqs dq40 dq41 dq42 dq43 dqs5 /dqs5 d5,d23( ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm cb0 cb1 cb2 cb3 dqs8 /dqs8 d8,d26( ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm dq4 dq5 dq6 dq7 dqs9 /dqs9 d9,d27( ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm / dqs dq12 dq13 dq14 dq15 dqs10 /dqs10 d10,d28(ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm dq20 dq21 dq22 dq23 dqs11 /dqs11 d11,d29(ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm / dqs dq28 dq29 dq30 dq31 dqs12 /dqs12 d12,d30(ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm dq52 dq53 dq54 dq55 dqs15 /dqs15 d15,d33(ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm / dqs dq60 dq61 dq62 dq63 dqs9 /dqs9 d9,d34( ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm dq36 dq37 dq38 dq39 dqs13 /dqs13 d13,d31(ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm / dqs dq44 dq45 dq46 dq47 dqs14 /dqs14 d14,d32(ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm cb4 cb5 cb6 cb7 dqs17 /dqs17 d17,d35(ddp) dqs /cs dm i/o0 i/o1 i/o2 i/o3 /dqs dqs /cs dm odt0 cke0 /pck7** /we 1:2 r e g i s t e r pck7** /reset** /cas /ras ba0 ? ba2 a0 ? a13 /s1* /rst /s0* rodt1 = > odt1: sdrams d18-d35 odt1 cke1 rodt0 = > odt0: sdrams d0-d17 rcke1 = > cke1: sdrams d18-d35 rcke0 = > cke0: sdrams d0-d17 /ra0 ? ra12 = > a0 -a12 : sdrams d0-d35 /rwe = > /we: sdrams d0-d35 /rcas = > /cas: sdrams d0-d35 /rras = > /ras: sdrams d0-d35 /rba0 ? rba2 = > ba0 -ba2 : sdrams d0-d35 /rs1 to /cs : sdrams d18 ? d35 /rs0 to /cs : sdrams d0 ? d17 notes: 1. register values are 22 ohms +/- 5%. 2. /rs0 and /rs1 alternate between the back and front sides of the dimm * /s0 connects to d/cs0 and /s1 connects to d/cs1 on both registers. ** /reset,pck7 and /pck7 connect to both registers. other signals connect to two registers. sa0 sa1 sa2 w p scl sda a0 a1 a2 serial pd scl u0 sda v dd spd v ref v dd /v ddq v ss serial pd do to d35 do to d35 do to d35 p l l oe ck0 /ck0 /reset pck0 to pck6, pck8,pck9 = > ck : sdramx d0-d35 /pck0 to /pck6, /pck8,/pck9 = > /ck : sdramx d0-d35 pck7 = > ck: register /pck7 = > /ck: register
rev. 1.0 / apr. 2005 10 1 240pin registered ddr2 sdram dimms absolute maximum ratings note : 1. stress greater than those listed may cause permanent dama ge to the device. this is a stress rating only, and device functional operation at or above the conditions indicated is not implied. expousure to absolute maximum rating conditions for extended periods may affect reliablility. operating conditions note : 1. up to 9850 ft. 2. if the dram case temperature is above 85 o c, the auto-refresh command in terval has to be reduced to trefi=3.9us. for measurement conditions of t case , please refer to the jedec document jesd51-2. dc operating conditions (sstl_1.8) note : 1. v ddq must be less than or equal to v dd . 2. peak to peak ac noise on v ref may not exeed +/-2% v ref (dc) 3. vtt of transmitting device must track vref of receiving device. parameter symbol value unit note voltage on v dd pin relative to vss v dd - 1.0 v ~ 2.3 v v 1 voltage on vddl pin relative to vss v ddl - 0.5 v ~ 2.3 v v 1 voltage on v ddq pin relative to vss v ddq - 0.5 v ~ 2.3 v v 1 voltage on any pin relative to vss v in, v out - 0.5 v ~ 2.3 v v 1 storage temperature t stg -50 ~ +100 o c 1 storage humidity(wit hout condensation) h stg 5 to 95 % 1 parameter symbol rating units notes dimm operating temperature(ambient) t opr 0 ~ +55 o c dimm barometric pressure(operating & storage) p bar 105 to 69 k pascal 1 dram component case temperature range t case 0 ~+95 o c 2 parameter symbol min max unit note power supply voltage v dd 1.7 1.9 v v ddl 1.7 1.9 v v ddq 1.7 1.9 v 1 input reference voltage v ref 0.49 x v ddq 0.51 x v ddq v2 eeprom supply voltage v ddspd 1.7 3.6 v termination voltage v tt v ref -0.04 v ref +0.04 v 3
rev. 1.0 / apr. 2005 11 1 240pin registered ddr2 sdram dimms input dc logic level input ac logic level ac input test conditions note : 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih(ac) min for rising edges and the range from v ref to v il(ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switchin g from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. parameter symbol min max unit note input high voltage v ih (dc) v ref + 0.125 v ddq + 0.3 v input low voltage v il (dc) -0.30 v ref - 0.125 v parameter symbol min max unit note ac input logic high v ih (ac) v ref + 0.250 - v ac input logic low v il (ac) -v ref - 0.250 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr < figure : ac input test signal waveform>
rev. 1.0 / apr. 2005 12 1 240pin registered ddr2 sdram dimms differential input ac logic level note : 1. v in (dc) specifies the allowable dc execution of eac h input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. v id (dc) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs or udqs) level and v cp is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equal to v ih (dc) - v il (dc). note : 1. v id (ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih (ac) - v il (ac). 2. the typical value of v ix (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ix (ac) is expected to track variations in v ddq . v ix (ac) indicates the voltage at whitch differential input signals must cross. differential ac ou tput parameters note: 1. the typical value of v ox (ac) is expected to be about 0.5 * v ddq of the transmitti ng device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the voltage at whitch di fferential output signals must cross. symbol parameter min. max. units note v id (ac) ac differential input voltage 0.5 v ddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * v ddq - 0.175 0.5 * v ddq + 0.175 v 2 symbol parameter min. max. units note v ox (ac) ac differential cross point voltage 0.5 * v ddq - 0.125 0.5 * v ddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels >
rev. 1.0 / apr. 2005 13 1 240pin registered ddr2 sdram dimms output buffer levels output ac test conditions note: 1. the vddq of the device under test is referenced. output dc current drive note: 1.v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt. 4. the values of i oh (dc) and i ol (dc) are based on the conditio ns given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating po int along a 21 ohm load line to define a convenient driver current for measurement. symbol parameter sstl_18 units notes v otr output timing measurement reference level 0.5 * v ddq v1 symbol parameter sstl_18 units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4
rev. 1.0 / apr. 2005 14 1 240pin registered ddr2 sdram dimms pin capacitance (vdd=1.8v,vddq=1.8v, ta=25 o c f=1mhz ) 1gb : hymp112r72[p]8 2gb : hymp125r72[p]8 2gb : hymp125r72[p]4 4gb : hymp351r72m[p]4 note : 1. pins not under test are tied to gnd. 2. these value are guaranteed by design and tested on a sample basis only. pin symbol min max unit ck0, ck 0 cck 7 11 pf cke, odt ci1 8 12 pf cs ci2 8 12 pf address, ras , cas , we ci3 8 12 pf dq, dm, dqs, dqs cio 6 9 pf pin symbol min max unit ck0, ck 0 cck 7 11 pf cke, odt ci1 8 12 pf cs ci2 10 15 pf address, ras , cas , we ci3 8 12 pf dq, dm, dqs, dqs cio 8 13 pf pin symbol min max unit ck0, ck 0 cck 7 11 pf cke, odt ci1 8 12 pf cs ci2 10 15 pf address, ras , cas , we ci3 8 12 pf dq, dm, dqs, dqs cio 6 9 pf pin symbol min max unit ck0, ck 0 cck 9.5 14 pf cke, odt ci1 10.5 16 pf cs ci2 10.5 16 pf address, ras , cas , we ci3 10.5 16 pf dq, dm, dqs, dqs cio 17 21 pf
rev. 1.0 / apr. 2005 15 1 240pin registered ddr2 sdram dimms idd specifications (t case : 0 to 95 o c) 1gb, 128m x 72 register ed dimm : hymp112r72[p]8 2gb, 256m x 72 register ed dimm : hymp125r72[p]8 note: 1. idd6 current alues are guaranted up to tcase of 85 o c max. symbol e3(ddr2 400@cl 3) c4(ddr2 533@cl 4) unit note idd0 1550 1640 ma idd1 1640 1730 ma idd2p 704 704 ma idd2q 1010 1100 ma idd2n 1055 1145 ma idd3p(f) 875 920 ma idd3p(s) 713 722 ma idd3n 1190 1280 ma idd4r 1820 2180 ma idd4w 1910 2270 ma idd5b 3080 3080 ma 1 idd6 522 522 ma idd7 2810 3350 ma symbol e3(ddr2 400@cl3) c4(ddr2 533@cl 4) unit note idd0 2090 2270 ma idd1 2180 2360 ma idd2p 758 758 ma idd2q 1370 1550 ma idd2n 1460 1640 ma idd3p(f) 1100 1190 ma idd3p(s) 776 794 ma idd3n 1730 1910 ma idd4r 2360 2810 ma idd4w 2450 2900 ma idd5b 3620 3710 ma idd6 594 594 ma 1 idd7 3350 3980 ma
rev. 1.0 / apr. 2005 16 1 240pin registered ddr2 sdram dimms 2gb, 256m x 72 register ed dimm : hymp125r72[p]4 4gb, 512m x 72 registered dimm : hymp351r72m[p]4 note : 1. idd6 current alues are guaranted up to tcase of 85 o c max. symbol e3(ddr2 400@cl 3) c4(ddr2 533@cl 4) unit note idd0 2450 2630 ma idd1 2630 2810 ma idd2p 758 758 ma idd2q 1370 1550 ma idd2n 1460 1640 ma idd3p(f) 1100 1190 ma idd3p(s) 776 794 ma idd3n 1730 1910 ma idd4r 2990 3710 ma idd4w 3170 3890 ma idd5b 5510 5510 ma idd6 476 476 ma 1 idd7 4970 6050 ma symbol e3(ddr2 400@cl 3) c4(ddr2 533@cl 4) unit note idd0 3530 3890 ma idd1 3710 4070 ma idd2p 866 866 ma idd2q 2090 2450 ma idd2n 2270 2630 ma idd3p(f) 1550 1730 ma idd3p(s) 902 938 ma idd3n 2810 3170 ma idd4r 4070 4970 ma idd4w 4250 5150 ma idd5b 6590 6770 ma idd6 738 738 ma 1 idd7 6050 7310 ma
rev. 1.0 / apr. 2005 17 1 240pin registered ddr2 sdram dimms idd meauarement conditions note: 1. idd specifications are tested after the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs, udqs, and udqs . idd values must be me t with all combinations of emrs bits 10 and 11. 5. definitions for idd low is defined as vin vilac(max) high is defined as vin vihac(min) stable is defined as inputs st able at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changi ng between high and low ever y other clock cycle (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer ( once per clock) for dq signals not including masks or strobes. symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t ras- min(idd);cke is high, cs is high between valid comma nds;address bus inputs are switching;data bus inputs are switching ma idd1 operating one bank active-read-precharge curren ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd) ; cke is high, cs is high between valid commands ; address bus inputs are switch ing ; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle ; t ck = t ck(idd) ; cke is low ; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs ar e stable; data bus inputs are float- ing fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp= t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid com- mands; address bus inputs are switching;; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and addres s bus inputs are switchi ng; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. idd6 current va lues are guaranted up to tcase of 85 o c max. ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; - refer to the following page for detailed timing conditions ma
rev. 1.0 / apr. 2005 18 1 240pin registered ddr2 sdram dimms electrical characteri stics & ac timings speed bins and cl,trcd,trp,trc and tras for corresponding bin ac timing parameters by speed grade speed ddr2-533 (c4) ddr2-400 (e3) unit bin(cl-trcd-trp) 4-4-4 3-3-3 parameter min min cas latency 4 3 tck trcd 15 15 ns trp 15 15 ns trc 60 55 ns tras 45 40 ns parameter symbol ddr2-400 ddr2-533 unit note min max min max data-out edge to clock edge skew tac -600 600 -500 500 ps dqs-out edge to clock edge skew tdqsck -500 500 -450 450 ns clock high level width tch 0.45 0.55 0.45 0.55 ck clock low level width tcl 0.45 0.55 0.45 0.55 ck clock half period thp min (tcl,tch) - min (tcl,tch) -ns system clock cycle time tck 5000 8000 3750 8000 ps dq and dm input setup time tds 150 - 100 - ps 1 dq and dm input hold time tdh 275 - 225 - ps 1 dq and dm input setup time(sin gle-ended strobe) tds1 25 - -25 - ps 1 dq and dm input hold time(single-ended strobe) tdh1 25 - -25 - ps 1 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse witdth for each input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance window from ck, /ck thz - tac max - tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps dqs-dq skew for dqs and associated dq signals tdqsq - 350 -300 ps dq hold skew factor tqhs - 450 -400 ps dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps first dqs latching transiti on to associated clock edge tdqss 0.25 +0.25 0.25 +0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck write preamble twpre 0.35 - 0.35 - tck
rev. 1.0 / apr. 2005 19 1 240pin registered ddr2 sdram dimms - continued - note : 1. for details and notes, please refer to the rele vant hynix component datasheet(hy5ps1g[4/8]31(l)f). 2. 0 c tcase 85 c 3. 85 c tcase 95 c parameter symbol ddr2-400 ddr2-533 unit note min max min max address and control input setup time tis 350 -250 - ps address and control input hold time tih 475 -375 - ps read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck auto-refresh to active/auto-refresh command period trfc 127.5 - 127.5 - ns row active to row active delay for 1kb page size trrd 7.5 - 7.5 - ns row active to row active delay for 2kb page size trrd 10 - 10 - ns four activate window for 1kb page size tfaw 37.5 - 37.5 - ns four activate window for 2kb page size tfaw 50 - 50 - ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal twr+trp - twr+trp - tck write to read command delay twtr 10 - 7.5 - ns internal read to precharge command delay trtp 7.5 7.5 ns exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al tck cke minimum pulse width (high and low pulse width) t cke 3 3 tck odt turn-on delay t aond 2 222tck odt turn-on t aon tac(min) tac(max)+1 tac(min) tac(max)+1 ns odt turn-on(power-down mode) t aonpd tac(min)+2 2tck+tac (max)+1 tac(min) +2 2tck+tac (max)+1 ns odt turn-off delay t aofd 2.5 2.5 2.5 2.5 tck odt turn-off t aof tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 ns odt turn-off (power-down mode) t aofpd tac(min)+2 2.5tck+tac( max)+1 tac(min)+2 2.5tck+tac( max)+1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck +tih tis+tck +tih ns average periodic refresh interval trefi - 7.8 - 7.8 us 2 trefi - 3.9 - 3.9 us 3
rev. 1.0 / apr. 2005 20 1 240pin registered ddr2 sdram dimms package outline 128mx72 (1 rank) - hymp112r72[p]8 note) all dimensions are typical millimeter scale unless otherw ise stated. front 30.0 4.00.1 133.35 63.0 5.175 5.175 55.0 5.0 back 0.8 0.05 1.0 0.20 detail of contacts a 2.50 0.20 detail of contacts b 2.50 1.50 0.10 3.80 5.00 detail-a detail-b 3.0 3.0 10.0 17.80 pll r e g i s t e r side 2. 7 max (front) 1. 27 0.10
rev. 1.0 / apr. 2005 21 1 240pin registered ddr2 sdram dimms package outline 256mx72 (2 ranks) - hymp125r72[p]8 note) all dimensions are typical millimeter scale unless otherw ise stated. front 30.0 4.00.1 133.35 63.0 5.175 5.175 55.0 5.0 back 0.8 0.05 1.0 0.20 detail of contacts a 2.50 0.20 detail of contacts b 2.50 1.50 0.10 3.80 5.00 detail-a detail-b side 4.0 max 1.27 0.10 3.0 3.0 10.0 17.80 r e g i s t e r pll r e g i s t e r
rev. 1.0 / apr. 2005 22 1 240pin registered ddr2 sdram dimms package outline 256mx72 (1 rank) - hymp125r72[p]4 note) all dimensions are typical millimeter scale unless otherw ise stated. front 30.0 4.00.1 133.35 63.0 5.175 5.175 55.0 5.0 back 0.8 0.05 1.0 0.20 detail of contacts a 2.50 0.20 detail of contacts b 2.50 1.50 0.10 3.80 5.00 detail-a detail-b side 4.0 max 1.27 0.10 3.0 3.0 10.0 17.80 r e g i s t e r pll r e g i s t e r
rev. 1.0 / apr. 2005 23 1 240pin registered ddr2 sdram dimms package outline 512mx72 (2 ranks) - hymp351r72m[p]4 note) all dimensions are typical millimeter scale unless otherw ise stated. front 30.0 4.00.1 133.35 63.0 5.175 5.175 55.0 5.0 back 0.8 0.05 1.0 0.20 detail of contacts a 2.50 0.20 detail of contacts b 2.50 1.50 0.10 3.80 5.00 detail-a detail-b 3.0 3.0 10.0 17.80 r e g i s t e r pll r e g i s t e r side 4. 0 max 1. 27 0.10
rev. 1.0 / apr. 2005 24 1 240pin registered ddr2 sdram dimms revision history revision history date remark 1.0 first version release data sheet coverage changed from an in dividual module part to a component based module family. dec. 2004 added vddl spec, corrected tds & tdh spec values. apr. 2005

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